According to well known prior art integrated circuit (IC) packaging methodologies, microelectronic dice are singulated and mounted using epoxy or other conventional means onto respective die pads or attach paddles of a leadframe strip. FIG. 1 shows a cross sectional view and a top view of a conventional leadframe package 100. Leadframe package 100 includes a die 110 mounted using die attach epoxy (or other means) 112 onto a die attach paddle 114. The leadframe 100 includes wire bonds 116 that are bonded between die 110 and peripheral leads or contacts 118. An overmold 120 encapsulates the die 110, epoxy 112, paddle 114, contacts 118, and wirebonds 116 as shown, leaving the bottom of contacts 118 exposed for joining with a motherboard.
Disadvantageously, as the length and width of the leadframe packages increases, such as for example, in the case of multi-silicon module packages, that is, in the case of a microelectronic package having a plurality of microelectronic components such as, for example, transistors, capacitors and memory devices, disposed horizontally on the package substrate, the reliability of solder joints between the motherboard and the leadframe becomes a problem. The length and width of a leadframe package may increase for a number of reasons. For example, increasing the number of microelectronic components to integrate added functionality to the leadframe package could increase a size of the package. In addition, an overall footprint of any number of microelectronic components to be integrated into the package could increase by virtue of functionality added to those components. One of the reasons for an adulteration of solder joint reliability is leadframe warping that occurs as the leadframe package dimensions increase. The warpage is typically a result of either (1) a mismatch between the coefficients of thermal expansion of the mold compound encapsulating the package components and the base metal, usually copper, onto which the leadframe package is built; (2) a mismatch between the coefficients of thermal expansion of the leadframe package substrate (for example, silicon) attached to the base metal; or (3) a mismatch between the coefficients of thermal expansion of the overmolded microelectronic device with respect to the underlying motherboard. With respect to point (1) above, when the mold material is provided onto the die, epoxy, paddle, contacts and wirebonds, it is thereafter allowed to cure, typically shrinking at a different rate than the base metal for the leadframe package, in this way bringing about a warpage of the resulting leadframe package. With respect to points (2) and (3) above, since the overmold, package substrate, base metal and motherboard material are made from different materials, they will react differently to the heat generated by the die. The resulting thermal stresses can create a warpage of the leadframe package. A warpage of the leadframe package can ultimately affect the reliability of solder joints joining the contacts of the leadframe package to the underlying motherboard. In particular, when the leadframe package is warped, it has poor coplanarity before being surface mounted onto a motherboard. The result can be poor solder joint formation or even incomplete solder joint formation with the motherboard causing electrical opens, since some joints will be taller while others will be shorter, causing inconsistent loading on joints.
The prior art fails to provide a method of improving solder joint reliability between a leadframe package and the underlying motherboard.